This patent description was copied from http://www.delphion.com/ , on 1 August 2002.

Title : US6421775: Interconnected processing nodes configurable as at least one non-uniform memory access (NUMA) data processing system

Country : US United States of America

Inventor : Brock, Bishop Chapman ; Austin, TX
Glasco, David Brian ; Austin, TX
Peterson, James Lyle ; Austin, TX
Rajamony, Ramakrishnan ; Austin, TX
Rockhold, Ronald Lynn ; Austin, TX

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Assignee : International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (approx. 33,182)
Published / Filed : July 16, 2002 / June 17, 1999

Application Number : US1999000335301

IPC Code : G06F 15/177; G06F 9/00; G06F 9/24; G06F 15/00;

U.S. Class : 713/001 ; 713/002 ; 712/028 ; 709/100 ;

Field of Search : 713/1;2 712/028 711/120,143,148,153 709/100

Priority Number :
June 17, 1999   US1999000335301

Abstract : A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.

Attorney, Agent or Firm : Salys, Casimer K.Bracewell & Patterson, L.L.P. ;

Primary / Assistant Examiners : Gaffin, Jeffrey ; Cao, Chu

First Claim : Show all 19 claims

What is claimed is:

1. A data processing system, comprising:

  • a system interconnect;
  • a plurality of processing nodes coupled to said system interconnect, each of said plurality of processing nodes containing at least one processor and data storage; and
  • boot code residing in a system memory in at least one of said plurality of processing nodes, wherein said boot code includes a configuration utility that, upon system reset, selectively configures said plurality of processing nodes into one of a single non-uniform memory access (NUMA) system and multiple independent data processing systems through communication via said system interconnect, and wherein said boot code boots an independent operating system in each configured data processing system, such that said boot code boots multiple independent operating systems when said configuration utility configures said plurality of processing nodes as a plurality of data processing systems.


         
U.S. References :   |  No patents reference this one   |  Backward references (13)   |  

Patent   Pub.Date   Inventor Assignee    Title
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  US6108764 2000-08 Baumgartner et al.  International Business Machines Corporation Non-uniform memory access (NUMA) data processing system with multiple caches concurrently holding data in a recent state from which data can be sourced by shared intervention
  US6148361 2000-11 Carpenter et al.  International Business Machines Corporation Interrupt architecture for a non-uniform memory access (NUMA) data processing system
  US6243794 2001-06 Casamatta  Bull HN Information Systems Italia S.p.A. Data-processing system with CC-NUMA (cache-coherent, non-uniform memory access) architecture and remote cache incorporated in local memory
  US6247109 2001-06 Kleinsorge et al.  Compaq Computer Corp. Dynamically assigning CPUs to different partitions each having an operation system instance in a shared memory space
  US6275907 2001-08 Baumgartner et al.  International Business Machines Corporation Reservation management in a non-uniform memory access (NUMA) data processing system
  US6347372 2002-02 Takashima et al.  Fujitsu Limited Multiprocessor control system, and a boot device and a boot control device used therein
         
Foreign References :
Publication Date IPC Code Assignee   Title
EP0780769 1997-06  G06F 12/08 SUN MICROSYSTEMS, INC. Hybrid numa coma caching system and methods for selecting between the caching modes  
EP0817076 1998-01  G06F 12/08 SUN MICROSYSTEMS, INC. A multiprocessing computer system employing local and global address spaces and multiple access modes  


Other References :
  • David Parry, Scalability in Computing for Today and Tomorrow, ARVLSI 1997.
  • RD 416099, Derwent Abstract for Research Disclosure, Dec. 1998.
  • Australian Patent Office Written Opinion, Dec. 5, 2001.