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Title: US7080214: Directory based support for function shipping in a multiprocessor system
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Country: US United States of America

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Inventor: Peterson, James Lyle; Austin, TX, United States of America
Rajamony, Ramakrishnan; Austin, TX, United States of America
Shafi, Hazim; Austin, TX, United States of America

Assignee: International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 2006-07-18 / 2003-10-16

Application Number: US2003000687261

IPC Code: Advanced: G06F 12/08;
Core: more...

ECLA Code: G06F12/08B4N; G06F12/08B4P2;

U.S. Class: 711/141; 711/147;

Field of Search: Non/00e

Priority Number:
2003-10-16  US2003000687261

Abstract:     A multiprocessor system includes a plurality of data processing nodes. Each node has a processor coupled to a system memory, a cache memory, and a cache directory. The cache directory contains cache coherency information for a predetermined range of system memory addresses. An interconnection enables the nodes to exchange messages. A node initiating a function shipping request identifies an intermediate destination directory based on a list of the function's operands and sends a message indicating the function and its corresponding operands to the identified destination directory. The destination cache directory determines a target node based, at least in part, on its cache coherency status information to reduce memory access latency by selecting a target node where all or some of the operands are valid in the local cache memory. The destination directory then ships the function to the target node over the interconnection.

Attorney, Agent or Firm: Salys, Casimer K. ; Dillon & Yudell LLP ;

Primary / Asst. Examiners: Verbrugge, Kevin;

INPADOC Legal Status: None          Buy Now: Family Legal Status Report

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First Claim:
Show all 20 claims
    1. A data processing node within a multi-node multiprocessor system, comprising:

a processor connected to a system memory having a predetermined range of memory addresses;

a cache memory connected to the processor; and

a cache directory containing coherency status information for the range of memory addresses, wherein the cache directory is enabled to receive a message from a home node of a function, the message being indicative of the function and a list of operands and wherein a memory address for at least one of the operands is in the range of memory addresses; and

wherein the cache directory is enabled to determine a target node based, at least in part, on the cache coherency status information and memory access latency evaluation and to ship the function to the determined target node for execution.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (6)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 18pp US5625811  1997-04 Bhide et al.  International Business Machines Corporation Method and system for database load balancing
Buy PDF- 17pp US5675791  1997-10 Bhide et al.  International Business Machines Corporation Method and system for database load balancing
Buy PDF- 21pp US6683850  2004-01 Dunning et al.  Intel Corporation Method and apparatus for controlling the flow of data between servers
Buy PDF- 14pp US20040117345  2004-06 Bamford et al.   Ownership reassignment in a shared-nothing database system
Buy PDF- 12pp US20040215639  2004-10 Bamford et al.   Dynamic reassignment of data ownership
Buy PDF- 11pp US20040215640  2004-10 Bamford et al.   Parallel recovery by non-failed nodes
       
Foreign References: None

Continuity Data:
Application Number Filed Notes

US2003000687261 2003-10-16  is a related to the prior publication
     US20050086438A1 issued 2005-04-21  Directory based support for function shipping in a multiprocessor system


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